As semiconductor technology evolves, additional processing engines are being integrated in a single package, and even onto a single die. For example, some processors may be architected to include multiple processor cores and at least one graphics engine (GE). The cores and the graphics engines may share a last level cache (LLC). As graphics processing is very memory intensive, the only viable solution is to allow it to share the last level cache with the core. However, contention between the core and GE for the cache/memory bandwidth may cause non-deterministic behavior that may either hurt core application performance or graphics processing ability. One solution is to statically partition the last level cache, but this has the drawback of inefficient cache use. For example, some applications may not be helped by a cache and can have various phases. Therefore more cache space may not improve their performance and at the same time can hurt GE's performance since it cannot use the core's partition.